In microcontroller-based, closed-loop control applications such as cost sensitive motor control and multi-channel power conversion applications, the microcontroller typically includes an Analog-to-Digital Converter (ADC) and a processor. The ADC is used to sample voltages and/or currents existing in the system being controlled. In some applications, these samples need to be taken at the same time or nearly at the same time because relationships between the quantities being measured are important. Accordingly, a set of related samples is taken, processing is then performed on the samples to calculate a control output, and then the control output is provided back to the system in order to control the system. This entire closed-loop sequence may need to be performed at a relatively rapid rate such as, for example, once every fifty microseconds or less.
In one conventional approach, several ADCs are provided so that the several ADCs can measure the required voltages and currents in parallel at the same time. This is generally a quite expensive solution due to the cost of providing multiple ADCs.
In another conventional approach, the microcontroller includes a single but relatively fast ADC. This ADC takes samples at the rate of, for example, one sample every microsecond. Samples are taken one at a time in series but due to the speed of the ADC the time delay between samples is acceptable. Due to the serial sampling, however, there remains less time for the processor to do the necessary processing on the samples before the end of the control loop cycle. In addition, the processor is generally interrupted after each ADC conversion is performed. In response to being interrupted, the processor switches contexts, reads the result of the ADC, stores the result, then starts the ADC in performing the next analog to digital conversion, and then switches contexts back in order to resume the processing task that it was performing before it was interrupted. Because these interruptions consume processing cycles, a relatively fast processor may be required in order to perform the processor's computational tasks in the time remaining. Providing the fast ADC and the fast processor may be undesirably expensive for some cost sensitive applications.
In another conventional approach, a DMA controller is provided in a Von Neumann architecture in order to offload the processor of the task of having to service the ADC. The DMA controller, however, competes with the processor for use of the main bus. Bus contention introduces unwanted complexities into the design of the control loop software. In addition, the DMA controller is often a large circuit and providing the DMA controller along with any necessary bus arbiter increases the size of the microcontroller die. A Harvard architecture can be employed so that the DMA controller can service the ADC over a second bus while the processor has uncontested use of the main bus, but providing such a Harvard architecture with the extra bus is also undesirably expensive.